Hello
using the CADI protocol provided by ARM fast models, I am able to connect trace 32 on a virtual platform embedding a model of Cortex R. Reading the Trace 32 command manual and the ARMv8-R debugger document, I've understood that I have to use commands TERM.METHOD ARMSWI and TERM.GATE in order to use ARM semihosting feature with TRACE 32. Addionnally, I have updated my embedded code , executing in AArch32 state, so that it uses SVC 0x123456 to authorize the debugger to trap the semihosting call. I have rewritten low level putc/getc function called by printf in order to generate the SVC 0x123456. Nevertheless, when debugging in step by step in Trace 32, I have checked that the SVC is executed, but nothing appears within the terminal created by TERM.GATE at the beginning of the session. Do I miss some configuration step in Trace 32 to allow the ARM semihosting working with my virtual target in Trace 32 ?
Many thanks for your help
Frederic
ARM semihosting with virtual target in TRACE 32 - Community / Debugging - Lauterbach Support
ARM semihosting with virtual target in TRACE 32 Awaiting Agent
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Lella Aicha Ayadi
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Hello Frederic,
We do provide demo for semi hosting emulation ~~/demo/arm/etc/semihosting_arm_emulation/armv8_aarch32/swisoft_armv8.cmm
Please note that Cortex-R52 is by default in HYP mode, and that SVC instructions do not work in HYP mode. To make it work, the SVC must be set using Register.Set M 0x13 command (line 38). Please try it and let me the findings.
In case you are still having problems, please send me the system information report about your TRACE32 configuration and the script you are using. The system information can be generated by selecting the TRACE32 menu 'Help' > 'Support' > 'System Information...', click 'Save to File' and send the resulting text file as an attachment to your e-mail.
Regards,
Aicha