Hi:
1 Environmental description:
1) interface definition: DAP2
2) Trace32 setting:
1. Open the shortcut of t32m51.exe;
2. Select TC3xx_SCR, DAP2 interface, and 10 MHz rate;
3) SCR Settings
1. Tricore and SCR are powered independently;
2. SCR operates through the XRAM space mode;
2 Question:
1) When Tricore is powered off and the SCR is operating normally, by attaching the SCR chip using Laubach and clicking "stop", it was found that the code was running at address 0x0, which does not match the expected result;
2) Some registers are not accessible;
3) The relevant documents for the Laubach XC800, except for
(debugger_xc800.pdf and xc800_app_ocds.pdf)
Please help me, expect your reply.
Hello Peng han,
This is a known bug of the SCR on TC3xx, if you start the SCR with PMSWCR4.SCRCFG = 02 ... 0F (OCDS Mode), and the debugger attaches to the SCR, this problem occurs.
In this scenario, The SCR does not set TRAP_EN = 1: In OCDS mode the SCR monitor program sets a breakpoint at address 0x0.
If TRAP_EN = 1, then the target application is stopped at this breakpoint (stopped at reset vector).
But if TRAP_EN = 0, then the byte at address 0x0 is not interpreted as a breakpoint instruction and the following opcodes are corrupted(which is the case here).
The behaviour of the program is in this case unpredictable. A workaround is to add a NOP at the start address(0x0). Otherwise the debugging makes problem and this must be done with a new start up code.
Best Regards,
Nada