There is a register called DBGDSCR (Debug Status and Control Register) which can be used for this purpose. In fact, if the debugger connects to the core, it will set the bit 14 "DBGDSCR.HDen" ("Halting debug-mode enable" bit). This bit is cleared on reset.

Cortex-M:

For stop mode debugging the debugger usually sets inside the DHCSR the C_DEBUGEN flag (bit 0). Stop mode debugging is usually the standard way to debug Arm cores using our tools. DHCSR is a debug register inside the SCS block of each Cortex-M core at address 0xE000EDF0. It should be readable by the target application, too.

But please be aware: the flag will be set immediately, when connecting using SYStem.Mode Up/Go/Attach and will be kept set even on SYStem.Down.