Yes. On Cortex‑A/R cores, the DBGDSCR (Debug Status and Control Register) can be used for this purpose. When a debugger connects to the core, it sets bit 14 (DBGDSCR.HDen, the “Halting debug‑mode enable” bit). This bit is cleared on reset.

On Cortex‑M cores, stop‑mode debugging is typically used, and in this case the debugger sets the C_DEBUGEN flag (bit 0) inside the DHCSR (Debug Halting Control and Status Register). DHCSR is part of the System Control Space (SCS) block at address 0xE000EDF0, and it should be readable by the target application as well.

Be aware that the flag is set immediately when connecting with SYStem.Mode Up/Go/Attach and remains set even after SYStem.Down.