FAQs by core architecture
- [Arm] Does TRACE32 need access to the CoreSight ROM table?
- [Arm] How to access the memory on Cortex-A/R on run-time?
- [Arm] Break command returns "emulation running"
- [Arm] Is it possible to attach to the target without resetting the onchip trace?
- Is it possible to set an on-chip breakpoint on a physical address for a processor with enabled MMU?
- [MPC5xxx] No debugger access due to a censored device
- [MPC5xxx] Impacts of the Nexus probe during energy measurement
- [PowerArchitecture] "emulation pod configuration error"
- [MPC5xxx] Why are sometimes certain messages not visible in the trace?
- [MPC5xxx] Why do I get power fail messages, despite target power is correct at the reference pin?
- [RISC-V] [HW-Designer] 'mcontrol' on-chip trigger supported combinations
- [RISC-V] Which standard RISC-V ISA extensions are supported?
- [RISC-V] [HW-Designer] Which versions of the RISC-V debug specification are supported?
- [RISC-V] [HW-Designer] Which ways of integrating a RISC-V debug module into a SoC are currently supported?
- [RISC-V] SYStem.Up / SYStem.Attach returns a fatal error
- [TriCore] MCDS commands locked
- [TriCore] Sometimes, after writing to cache memory using the debugger the data reverts back to the original value
- [TriCore] Core local addressing and "ambiguous symbol" error
- [TriCore] Which Debug Protocol should I use: DAP or JTAG?
- [TriCore] When the CPU has halted the debugger shows "stopped by swevt" or "stopped by tr0evt"
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TRACE32 Arm Executable Consolidation
Published: Nov 27, 2024
0Sep 23, 2025