FAQs by core architecture
- [Arm] Does TRACE32 need access to the CoreSight ROM table?
- [Arm] How to access the memory on Cortex-A/R on run-time?
- [Arm] Break command returns "emulation running"
- [Arm] Can I attach to an Arm target without resetting the on-chip trace?
- Can I set an on-chip breakpoint on a physical address when the MMU is enabled?
- [MPC85xx][Linux] Breakpoint are not working properly for e500 cores
- [MPC5xxx] Can the Nexus port totally be disabled?
- [MPC5xxx] Impact on processing power when using TRACE32
- [MPC5xxx] The external bus interface (EBI) fails when the debugger is connected
- [MPC5xxx] No debugger access due to a censored device
- [RISC-V] [HW-Designer] 'mcontrol' on-chip trigger supported combinations
- [RISC-V] Which standard RISC-V ISA extensions are supported?
- [RISC-V] [HW-Designer] Which versions of the RISC-V debug specification are supported?
- [RISC-V] [HW-Designer] Which ways of integrating a RISC-V debug module into a SoC are currently supported?
- [RISC-V] SYStem.Up / SYStem.Attach returns a fatal error
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TRACE32 Arm Executable Consolidation
Published: Nov 27, 2024
0Aug 13, 2026