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Knowledgebase
FAQs by core architecture
FAQs by core architecture
ARC
(3)
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[ARC] How can I see the auxiliary registers?
[ARC] Error message "debug port fail"
View all articles in ARC
Arm
(19)
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[Arm] Does TRACE32 need access to the CoreSight ROM table?
[Arm] How to access the memory on Cortex-A/R on run-time?
[Arm] Break command returns "emulation running"
[Arm] SYStem.DETECT sets the CPU to "NONE"
[Arm] DRAM memory flickering
[Arm] SYStem.Up / SYStem.Attach returns "debug port fail"
[Arm] What is the meaning of the state running (...)?
TRACE32 Arm Executable Consolidation
What is the difference between LA-2729 and LA-3770?
View all articles in Arm
MPC5xxx / SPC5xx
(16)
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[MPC5xxx] Can the Nexus port totally be disabled?
[MPC5xxx] Is 16 bit MDO operation supported?
[MPC5xxx] How to manage external watchdog timer control?
[MPC5xxx] Impact on processing power when using TRACE32
[MPC5xxx] No debugger access due to a censored device
[PowerArchitecture] "emulation pod configuration error"
[MPC5xxx] Debugger fails to connect to an XPC56XX EVB?
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RH850
(5)
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[RH850] SYStem.Up / SYStem.Attach returns "debug port fail"
Is it possible to debug RH850 using a V850 debug cable?
Impact of disabling this RDY pin in RH850 target
[RH850] Toggling Data Flash values
Does RH850 targets support memory access during runtime?
View all articles in RH850
RISC-V
(11)
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[RISC-V] Which RISC-V base ISAs are supported?
[RISC-V] SYStem.Up / SYStem.Attach returns a fatal error
Trace support for PolarFire® SoC (RISC-V + FPGA)
View all articles in RISC-V
TriCore
(12)
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[TriCore] MCDS commands locked
[TriCore] Which Debug Protocol should I use: DAP or JTAG?
[TriCore] Debugging Safety-Critical Applications
[TriCore] CombiProbe for TriCore Use Cases
View all articles in TriCore
Intel® x86/x64
(1)
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View all articles in Intel® x86/x64
